Flat Panel Display Driver Method and System

ABSTRACT

Methods and systems are described for enabling display system data transmission during use. An integrated circuit package includes input interface circuitry configured to receive an audio-video data stream having a video signal and timing information and timing extraction circuitry that can identify blanking patterns for the video signal. The package includes input processing circuitry for receiving audio-video signal and converting the audio-video data stream input into a low voltage differential signal (LVDS). The package includes a timing controller having timing extraction circuitry, a set of symbol buffers, a scheduler, and timing control circuitry. All configured to implement LVDS data transfer and in some implementation enable point to point data transfer from data buffers to associated column drivers.

CROSS REFERENCE TO RELATED APPLICATIONS

This patent application takes priority under 35 U.S.C. 119(e) to (i) U.S. Provisional Patent Application No. 61/177,963, filed on May 13, 2009 (Attorney Docket No. GENSP220P) entitled “Flat Panel Display Driver Method and System” by Osamu Kobayashi, which is hereby incorporated by reference in its entirety. Additionally, this patent application is related U.S. patent application Ser. No. 12/711,597, filed on Feb. 24, 2010 (Attorney Docket No. GENSP215) entitled “Method and Apparatus For Power Saving During Video Blanking Periods” by Kobayashi et al., which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present invention relates generally to communication methodologies and systems enabling display devices to transmit and display data during regular modes of operation. More particularly, methods, software, hardware, and systems are described for achieving point to point data delivery for the display of audio-video signal in a display device.

BACKGROUND OF THE INVENTION

Currently, multimedia networks are relatively unsophisticated in their in transmitting video data to column drivers in display devices. As computers, displays, laptops, electronic notebooks, and other devices transmit and use more and more multimedia data, the need for fast and efficient data transfer hardware and methodologies in the associated display devices increases.

In existing display systems and devices, video signals are transmitted to display devices for display. Such video signals include a pattern of active signals and interspersed with blanking periods. During the active periods signal information is provided containing displayable information. The blanking periods that accompany the active periods include horizontal blanking periods which demarcate line ends for the video signal. They also include horizontal blanking periods which are generally longer and demarcate frame boundaries for the video signal. During the blanking periods displayable signal is not provided.

During the active portion of the video signal, the transmitted displayable video information requires a significant amount of power consumption. The blanking periods also require a non-trivial amount of power in current implementations. In a low power usage environment, ways of reducing power consumption in all areas can be very advantageous.

While existing systems and methods work well for many applications, there is an increasing demand for display methodologies that enable increased power savings in a wider range of operational circumstance and higher efficiencies of multimedia data transport with far greater capacity to fully enjoy the benefits of modern multimedia equipment, software and devices. This disclosure addresses some of those needs.

SUMMARY OF THE INVENTION

In one aspect, an integrated circuit package configured to operate in a display device. The package is configured to operate in a video display device. The package includes input interface circuitry for receiving an audio-video signal comprising an audio-video data stream having embedded timing information associated with the audio-video data of the data stream. Additionally, the package includes input processing circuitry for receiving audio-video signal and converting the audio-video data stream input into a low voltage differential signal (LVDS) that is output as a differential audio-video signal. The package includes a timing controller having timing extraction circuitry, a set of symbol buffers, a scheduler, and timing control circuitry. The timing extraction circuitry is configured for receiving the differential audio-video signal and enabling the identification of timing patterns in the received signal using the embedded timing information. The symbol buffers are arranged to receive data symbols that comprise the signal. The scheduler is configured to populate the symbol buffers with said data symbols in a pattern consistent with the embedded timing information. The timing control circuitry is configured to support a display wherein the timing control circuitry is arranged to forward the data symbols from the buffers at a specified time. In some cases the specified time is associated with characteristics of the display device. Moreover, the package can be configured to enable direct point to point connection between the buffers and each associated one of a set of column drivers of a display.

In another aspect the invention teaches a method of processing video data in an audio-video system. The method involves receiving an audio-video data stream including video signal and embedded timing information associated with the audio-video data. The audio-video data stream is converted into a low voltage differential signal (LVDS) and a timing pattern is identified for the audio video data using the embedded timing information. A set of symbol buffers is populated with said data symbols in a pattern consistent with the embedded timing information. The data symbols are forwarded from the symbol buffers to a display device. In a related aspect, the forwarding can be a direct point to point forwarding from the buffers to each associated column driver of a display.

In another aspect, the invention describes a computer implementable method for transmitting audio video data, the method embodied on a tangible computer readable media and comprising computer readable instructions. Including instructions for receiving an audio-video data stream having including video signal and embedded timing information associated with the audio-video data of the data stream. Including instructions for converting the audio-video data stream input into a low voltage differential signal (LVDS). Including instructions for identifying a timing pattern for the data stream or differential signal using the embedded timing information. Including instructions for populating a set of symbol buffers with data symbols in a pattern consistent with the embedded timing information and including instructions for forwarding said data symbols from the symbol buffers to a display device. In a related aspect, computer readable instructions for enabling point to point data transport between a buffer and its associated column driver can also be provided.

General aspects of the invention include, but are not limited to methods, systems, apparatus, and computer program products for enabling data transfer and display in display systems and devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention and the advantages thereof may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates a simplified embodiment of a display system networked with a multi-media source device.

FIG. 2 illustrates a timing diagram illustrating the blanking intervals and LVDS cycle that can be used to regulate power saving in a display device in accordance with the principles of the invention.

FIG. 3 is a timing diagram that illustrates power consumption in a display device over time.

FIG. 4 is a timing diagram that illustrates the reduced power consumption realized by the application of power saving embodiments operating in accordance with the principles of the invention of the invention.

FIG. 5 is a system diagram showing the various blocks of a display system implemented in accordance with the principles of the invention.

FIG. 6A is a system diagram illustrating one approach for obtaining blanking cycle information and then applying it to a power saving application in accordance with the principles of the invention.

FIGS. 6B and 6C show a system diagram illustrating another approach for obtaining blanking cycle information from an encoded MSA and then applying it to a power saving application in accordance with the principles of the invention.

FIG. 7 illustrates a controlled approach to power saving using a system diagram to show how one embodiment of the invention can implement power saving in accordance with the principles of the invention.

FIG. 8 is a flow diagram illustrating one approach to implementing power saving in a display system in accordance with the principles of the invention.

FIG. 9 provides a simplified schematic depiction of one embodiment having a reduced connection interface.

In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Reference is made to particular embodiments of the invention. Examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with particular embodiments, it will be understood that it is not intended to limit the invention to the described embodiments. To contrary, the disclosure is intended to extend to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.

Aspects of the invention pertain to methods and systems for enabling power saving in display devices in electronic systems to include multimedia systems. In the ordinary operation of such systems, a display device is coupled (directly or indirectly) with a source device that provides video content. FIG. 1 illustrates a highly simplified example of multimedia network 100 comprising a source device 101 and a display 102 linked by a data link 103.

Example source devices 101 include, but are not limited to any device capable of producing or transmitting video content. In embodiments of this invention, the video content shall be interpreted broadly to encompass any video data configured in any data format. Accordingly, such video content can include, but is not limited to, video, image data, animation, text, audio (sound, music, etc.) and interactive content, as well as combinations of all of the foregoing. Again, in general, source devices 101 are those devices that capture, generate, or transmit multimedia (to include video) content. Particular examples include, but are not limited to set top boxes, DVD players, cameras, video recorders, game platforms, computers, HD video devices, VCR devices, radio, satellite boxes, music players, content capture and content generation devices, and many other such source devices beyond those referenced above. Such devices can transmit video data in a number or different data formats, including, but not limited to VGA (and its analogs), HDMI, DisplayPort, CVBS, as well as many other formats.

Display 102 embodiments of the invention include display support circuitry 104 that couple the link 103 (and therefore the source 101) to the display 102. The display support circuitry 104 enables communication between the display 102 and the source 101.

In embodiments of the invention, the source 101 outputs an audio-video data stream having video signal and associated timing information. FIG. 2 includes a schematic depiction of a video data stream in accordance with the principles of the invention. FIG. 2 is a schematic depiction of a portion of a video data stream 200 transmitted perhaps to the display 102 of FIG. 1. The depicted portions of stream 200 schematically depict a blanking cycle for a video signal. Portions 201 define portions of the signal containing valid video data. Also shown are the horizontal blanking intervals (HBI or H-blanking) 202 which occur at regular intervals. Also shown are the vertical blanking intervals (VBI or V-blanking) 202 which occur at regular intervals and define video frame boundaries. Stream 210 is a depiction of the blanking cycle described using differential signaling. The portions 212 associated with the V-blanking intervals contain no data or non-video data. Such non-video data can comprise useful information or nothing at all.

A number of packet based delivery systems are suitable for use in accordance with the principles of the invention. In one example, such a packet based delivery and communication scheme is described in U.S. patent application Ser. No. 10/726,794 entitled “PACKET BASED VIDEO DISPLAY INTERFACE AND METHODS OF USE THEREOF” (Attorney Docket No. GENSP013) filed Dec. 2, 2003. This disclosure is incorporated by reference herein for all purposes and describes an approach to packet based communications in accordance with some embodiments of the invention.

Associated FIG. 3 depicts power consumption during the same cycle as described in FIG. 2. The power consumption is greatest during the valid data transmission intervals 301 and drops significantly during the blanking cycles 302, 303. Under current implementations the power consumption during these blanking intervals is still quite substantial. Using current approaches, this baseline level 304 of power consumption is helpful in preventing noise spikes during switching and also addresses EMI (electro-magnetic interference) problems during such spikes.

The inventors propose that the power during the blanking intervals be substantially reduced. By shutting down, or selectively reducing power to, selected circuit elements of the display substantial power savings can be obtained even during the operation of a display device. FIG. 4 is a simplified illustration of such power savings. In this example, the power in the blanking intervals 401, 403 is reduced. In the depicted embodiment, the power usage is reduced to zero. In other embodiments, the power reduction need not be so extreme. In any case, the average power is reduced enabling a power saving that is substantially greater than the prior art.

One apparatus embodiment for implementing power saving is illustrated in FIG. 5. A depicted arrangement of components includes an audio-video source device 501 connected to input interface circuitry 511 using a data link 502. The source 501 can be one of many different type audio-video systems. DVD players, set top boxes, game consoles, and a huge array of other devices known to persons of ordinary skill in the art. Such devices 501 can transmit data in accord with any of a number of different data formats and/or interfaces including, but not limited to HDMI, CVBS, VGA, DisplayPort and many other signal formats. The input interface circuitry 511 can also be configured to receive inputs from keyboards, USB ports, IR actuated devices (e.g., remote control interfaces), and so on. In the depicted arrangement, the source transmits an audio-video data stream 503 that includes audio signal and encoded timing information. In one example format, the data stream 503 is encoded in an 8b/10b format. Moreover, this transmission format can be a packet based format. The input interface circuitry 511 is typically configured as a system-on-a-chip designed to convert the received data into a format or a timing compatible with a format or timing of a display panel 521. In some embodiments, a display system will have more than one set of input interface circuitry 511 depending on the characteristics of the panel 521 or the network that the panel 521 belongs to. For example, the panel 521 can be configured to operate at 60 Hz, 120 Hz or even 240 Hz. Typically, a separate input interface processor 511 is provided for each operating frequency.

In some embodiments, the audio-video data stream 503 is an 8b/10b encoded signal received by the input interface circuitry 511. In some embodiments, the 8B/10B signal is transmitted (as 504) to a timing controller 523 without modification. Alternatively, can be converted to an 8 bit signal and then transmitted. Also, in some embodiments the interface circuitry 511 can convert the signal to a differential signal such as a low voltage differential signal (LVDS). In other embodiments, the audio-video data stream 503 can be converted to other formats.

The input interface circuitry 511 is coupled to a timing controller (TCON) 523 of the panel 521 with a data link 512. The data stream 504 output from the interface circuitry 511 is received by the TCON 523 which processes the data and then outputs the information to an array of column drivers 522 which control the display of data on the panel 521. It should be noted that the TCON can receive the 8 B/10B coded signal or a decoded 8 bit signal as well as differential signal from the input interface circuitry 511 as well as other non-differential signals. In addition, the TCON 523 transmits video information to the column drivers 522 of the panel 522. The information can be transmitted in 8B/10B format, also, advantageously, it can be transmitted in a LVDS format. Other formats and encoding can be used. The inventors point out that the TCON and its function can be embodied in a system of a chip construction. In a related point, the applicants point out that the entire system 511, 512, 523, can be integrated onto a single chip in a system on a chip fashion if so desired.

In accord with the present invention, power saving can be achieved by selectively turning off of various systems and circuitry during operation. In particular, these systems are turned off (or supplied less power) during the blanking intervals. It is expressly pointed out that the timing information can be obtained or identified at the input interface 511 or at the timing controller 523. Moreover, that the power saving can be implemented at the input interface 511 or at the timing controller 523.

As further explained with respect to FIG. 6A, a first power saving embodiment is described. A source device 501 sends an audio-video data stream 503 in source data format over a data link 502 to an embodiment of input interface circuitry 511A. The data stream 503 includes video signal and timing data. In the depicted embodiment, the input interface circuitry 511A receives the data stream 503 and then decodes it to determine the blanking cycle for the decoded video signal which is schematically depicted as 503A. Timing extraction circuitry reads the data stream and extracts the timing information usable for identifying a blanking parent. The timing extraction circuitry can form part of the input interface 511 and also can form part of the timing controllers 523. In this embodiment, the timing information is obtained by identifying the blanking start (BS) symbols 504A and blanking end (BE) symbols 505A for the decoded signal 503A. These start and end symbols (504A, 505A) comprise timing information that can be used to establish a blanking cycle for the received data signal 504A. This timing information can be used to control the activity of the TCON 523. In particular, it can be used to generate a timing signal (schematically depicted by 602) that is provided to a TCON 523 which enables, among other things, control of the line buffers and the shift registers and the column drivers 522. Also, it controls the operation of the frame buffers and associated circuitry of the panel 521.

In this embodiment, the timing signal 602 is generated by the processing circuitry of the input interface circuitry 511A. In one example, the signal 602 can be received or generated by a GPIO 611. For example, the timing signal 602 can be sent via an output pin of the GPIO 611 which is coupled 601 with a pin of a GPIO 612 of the TCON 523A.

The timing signal 602 can now be used at the panel 521 to implement power saving. During the blanking cycle, the TCON 523A can for example be turned off. The column drivers can be turned off or receive reduced power. Other panel systems or logic blocks can also be turned off during the blanking periods of the timing signal 602 if desired.

The inventors point out that the input interface circuitry 511 (511A, 511B) can be configured to transmit the received data stream 503 in its original format or convert it to another format. One particularly advantageous format suggested by the inventors is a low voltage differential signal (LVDS) which has numerous power saving advantages and reduced EMI properties.

In another approach, outlined briefly with respect to a discussion of FIG. 6C, the data received from the source device 501 can include power saving instructions and/or include timing information encoded in a somewhat different manner. Again, using the timing information, power saving can be achieved by the selective turning off of various systems and circuitry during the blanking intervals.

With continued reference to FIG. 6B, source device 501 sends an audio-video data stream 503 in source data format over a data link 502 to an embodiment of input interface circuitry 511B. The data stream 503 includes video signal and timing data. However, in the depicted embodiment the timing information is encoded into a Main Stream Attribute (MSA) packet(s) of a data stream 503. Examples of such approaches for formatting such MSA packets and the data transmission methodologies associated therewith are explained in greater detail in, for example, in U.S. patent application Ser. No. 10/726,794 entitled “PACKET BASED VIDEO DISPLAY INTERFACE AND METHODS OF USE THEREOF” (Attorney Docket No. GENSP013) filed Dec. 2, 2003 already incorporated herein.

During a handshake protocol between the source 501 and display, the input interface circuitry 511B receives configuration data from the source during the protocol. The circuitry 511A decodes the data and uses information in the data stream to decode the received signal. This enables the circuitry 511A and/or the TCON 523A to be correctly configured to properly display the video signal. In one particular approach, the necessary configuration is provided to the input interface circuitry 511B in a MSA packet that is decoded in the handshake protocol. Specific to this embodiment, the MSA includes timing information that can be used to identify the timing for the blanking intervals.

The input interface circuitry 511B receives the data stream 503 and decodes the MSA to determine the blanking cycle for the decoded video signal which is schematically depicted as 503B. As shown in FIG. 6C, in one embodiment, the data stream 503B comprises a stream of transfer units 621 transmitted in the active portion of the data stream. This is broken up by the vertical and horizontal blanking intervals. Here, the MSA 622 is inserted as one or more data packets in a vertical blanking interval 623. As before, the blanking intervals are delineated by blanking start (BS) and blanking end (BE) markers. The remainder of the blanking interval 623 can contain other non-displayed data or information or can be filled with dummy data.

The MSA can comprise timing information that can be used to establish a blanking cycle for the received data signal. As before, this timing information contained with in the MSA can be used to control the activity of the TCON 523B. In particular, it can be used to generate a timing signal (schematically depicted by 604) that is provided to a TCON 523B which enables, among other things, control of the line buffers and the shift registers and the column drivers 522 as well as the TCON itself. Also, it controls the operation of the frame buffers and associated circuitry of the panel 521.

In this embodiment, the timing information can be encoded simply within the MSA 622. In one example, the MSA can include information defining a format it can be coded as follows. A timing pattern can be indicated. In one example, 1080p (or other display format) or some other format can be designated. A total vertical period (V_(total)) can be specified. For example, using a 1080 signal, V_(total) can be characterized as 1125 lines with a displayable height V_(height) of 1080 for vertical blanking Vblank of 45 line periods. Similarly, a total horizontal period (H_(total)) can be specified. For example, using a 1080 signal, H_(total) can be 2200 pixels with a displayable width H_(width) of 1920 pixels such that the Hblank period is 300 pixels. This timing is also tied to the refresh rates and capabilities of the panel. Many different approaches could be used.

During the blanking periods portions of the circuitry can be turned off. Referring briefly to FIG. 7, an audio-video source device 501 supplies data (including video data and associated timing information) to input interface circuitry 511 using a data link. The input interface circuitry 511 is typically configured as a system-on-a-chip designed to convert the received data into a format or a timing compatible with a format or timing of a display panel 521. In some embodiments, the interface circuitry 511 forms part of a display device 701. Alternatively (as shown here), it is not required to be integral to the device 701. The input interface circuitry 511 includes signal transmission circuitry 711 enabling transmission of the data stream to the timing controller 523 of the display device 701. The timing controller 523 includes receiver circuitry 721 for receiving the signal and timing information from the input interface circuitry 511. The timing controller 523 includes a plurality of signal transmitters 712 transmitting video data to the plurality of column drivers 522 of the display panel 521. Each column driver 522 includes receiver circuitry 722 for receiving the signal and timing information from the controller 523. The timing controller 523 and its concomitant circuitry (e.g., 712, 721, and so on) can be configured as a system on a chip. Each of the transmitters 711, 712 and receivers 721, 722 consume power whether they are sending valid data or not. These devices consume most of the power budget. Thus, power saving can be achieved in accordance with the principles of the invention by turning off some or all of the transmitters 711, 712 and receivers 721, 722 during the blanking periods.

The prior portions of this patent have disclosed methods for identifying the blanking periods. The transmitters 711, 712 and receivers 721, 722 as well as other elements and logic blocks (e.g., the column drivers 522) can be turned off during these identified blanking periods. Importantly, some, all, or none of these components can be turned off to obtain varying levels of power savings. The components are turned back on when they are needed to process, transmit, receive, or otherwise interact with data. This power saving can be specified as an automatic response forming part of the instruction set that operates the input interface circuitry 511, the timing controllers 523, or the column drivers 522. Also, the power can be turned off in accordance with power off instructions provided by the source 501 or encoded into the data stream itself.

Also, as pointed out previously, this power saving can be achieved using systems where the communication between the TCON 523 and the column drivers 522 is achieved with differential signaling. For example, the TCON 523 can transmit data to the column drivers 522 as low voltage differential signals (LVDS). In one embodiment, the LVDS can be delivered in a serial data stream to all of the column drivers. Such an LVDS signal is compliant with the TIA/EIA 644 standard. Modes of operation of such systems are known in the art. For example, a Fairchild Semiconductor Application Note entitled “AN-5017 LVDS Fundamentals” dated December 2000, available at http://www.fairchildsemi.com/an/AN/AN-5017.pdf is instructive and hereby incorporated by reference.

For increased speed, the LVDS can be configured with a transmitter coupled with a plurality of column drivers in a multi-drop LVDS connection. Such arrangements are also known in the industry. For example, a Texas Instruments Application Report by Elliott Cole entitled “LVDS Multidrop Connections” dated February 2002, available at http://focus.ti.com/lit/an/slla054a/slla054a.pdf is also incorporated by reference.

In another implementation, each transmitter 712 of the timing controller 523 is coupled with an associated column driver 722 in a parallel arrangement of point-to-point LVDS connections. In another approach, the transmitters can be coupled with each column driver using a multi-channel packet based communication connection with embedded self-clock. Each channel being characterized by uni-directional data pairs in a main link. Such a link can also feature a bi-directional auxiliary channel. One example of such a link is a link compatible with the DisplayPort family of connectors. In this implementation the transmitted data can have 8B/10B channel coding.

The inventors point out that the TCON (523, 523A, 523B) can be configured as a system on a chip package. Also, the input interface circuitry 511 and the TCON (e.g., 523, 523A, 523B) can be integrated together in a single system on a chip package.

FIG. 8 depicts one example mode of operation for aspects of the invention. A process 800 for achieving power saving during the operation is described. An audio-video data stream is received by a display device (Step 801). As indicated above, audio-video data stream (e.g., 503) includes an audio-video signal and timing information. The data can be in any format, but in one embodiment is subject 8B/10B encoding. The receiving device (typically a display device, or circuitry ancillary to a display) identifies the blanking pattern of the audio video data (Step 803). This can be achieved by a direct read of the blanking pattern (i.e., processing the BS, BE indicators) to generate the blanking pattern. This can also be achieved by decoding of timing information encoded in MSA packets of the audio-video signal. These can be read and translated into a blanking pattern associated with the video signal. Details of some embodiments of these approaches have been disclosed in fuller detail in the preceding paragraphs. The inventors point out that other methods of determining the blanking pattern can also be employed.

Power saving is then implemented (Step 805). In one embodiment, power saving instructions can be employed to reduce display system power consumption during the blanking intervals of the audio video signal. Various system components of the display system are simply powered down during the blanking interval and then powered up again for operation during the active intervals between the blanking intervals. Example system blocks that can be powered down during the operation of the display include, but are not limited to the interface circuitry 511 (e.g., 511A, 511B) the TCON 523 (e.g., 523A, 523B), the column drivers 522, the receivers and transmitters (e.g., 711, 712, 721, 722). These power down instructions can be simply standardized as part of the normal display system operation. In other words, power to selected display systems can be temporarily terminated during blanking as part of the ordinary system operation. Also, specific power down instructions can be sent to a display device as part of the instructions contained in a data stream. Moreover, it can be configured to be adjusted as part of set up operations. Also, such instructions can be coded into the audio video data if desired. Thus, the power saving process can be automatic, selective, adjustable, and be determined remotely as instructions forming part of the audio-video data. Such power save instructions can be written into the firmware of the display systems or chips or can be part of the system software.

The inventor points out that another advantage of using the data encoded as a stream of LVDS packages (having embedded timing information) can be used to simplify data transmission in timing controller circuitry. This can cut down vastly on the number of connections required between a timing controller and column drivers of the display. For example, in a display using 8 column drivers in an ordinary multidrop configuration, each column driver will require 22 electrical lines (16 data lines, perhaps 4 column driver control signals and two clock lines). The EMI problems involved with such a high contact density are substantial. One of the advantages of the present invention is that the embedded timing information obviates the need for clock lines. Additionally, the simple LVDS arrangement seriously reduces the number of connections necessary to transmit data. Using the currently disclosed invention, the number of connections can be reduced to just two per column driver (just enough to provide the differential signal).

FIG. 9 provides a simplified schematic depiction of one embodiment having a reduced connection interface. In the depicted embodiment a point to point connection between symbol buffers and their associated column drivers can be achieved. This embodiment is similar to earlier described embodiments but includes some distinguishing features. To begin, source data 905 is received at input interface circuitry 911. Then it is input into a timing controller (TCON) 923 which can output differential signal to the column drivers 922 in a multiplicity of point to point connections. The input data stream 905 can be received from a number of different sources and configured in any of the formats previously described as well as others not so enumerated. As before, the original interface signal 905 can be formatted in a number of different formats including differential and non-differential signals. In one non-limiting example, the data comprises data with embedded timing information (thus obviating the need for a clock signal). For example an 8B/10B encoded video signal can be used.

As described above, the input interface 911 can be configured to receive the input 905 and then forward the information 906 to a timing extraction unit 921 configured to extract timing information and establish the frame and line refresh cycles. As also indicated above, this feature can also be performed by the interface 911 itself depending on the configuration. The interface 911 or the timing extractor 921 (or other circuitry) can be configured to convert the signal into a differential signal. A GPIO unit could be used to accomplish such a conversation to a differential signal (e.g., a LVDS signal). This signal can be output as differential signal 907 that can be received by a scheduler 925.

The scheduler 925 uses the embedded timing information as well as other information encoded into the data 907 to arrange the data into streams of data associated with video lines and frames. This data is then forwarded to an array of symbol buffers 927. In one example implementation, the video data is arranged as a series of video data lines, with each data line divided into portions 928. Each portion being sent to a respective symbol buffer 927. In this way, several lines of data can be sent to the symbol buffers 927. The data can be fed out, line at a time to the column drivers 922 of a display device. For example, a single line of data can be stored as a series of data portions 928 a extending across the several buffers 927.

The data 928 can then be transported, line at a time, to the column drivers 922. This can be done using a transmitter that forms part of the symbol buffer 927 or using another transmission approach. The numbers of lines that can be stored is dictated generally by the size of the buffers 927. The rate at which each line is transferred to the column drivers is controlled timing control circuitry 929 of the TCON 923. The controller 929 typically controls the shift registers and memory structures of the buffers 927. In one implementation, the scheduler 925 transports the data portions 928 to the buffers 927 using a pair of lines 931 configured to transmit LVDS signal. This facilitates low power usage, simplifies circuit design, and reduces EMI difficulties. Thus, the buffers 927 can be continuously populated by data portions 928 supplied by the scheduler 925.

One particularly advantageous feature of this approach is its ready adaptability to a true point-to-point data connection with the column drivers 922 of a display device. This enables a set of parallel connections between each symbol buffer 927 and its associated column driver 922. Due to the use of differential signaling, the connections between buffers and column drivers are simplified to a pair of connectors 932. As before, this simplifies circuit design, drives down power usage, and reduces EMI problems. Additionally, the use of true point to point communications generates faster and more efficient population of the buffers.

In addition, embodiments of the present invention further relate to integrated circuits and chips (including system on a chip (SOC)) and/or chip sets. By way of example, each of the devices described herein may include an integrated circuit chip or SOC for use in implementing the described embodiments and similar embodiments. Embodiments may also relate to computer storage products with a computer-readable medium that has computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of tangible computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor. In addition to chips, chip systems, and chip sets, the invention can be embodied as firmware written to said chips and suitable for performing the processes just described.

The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the invention. Thus, the foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. It will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents. 

1.-26. (canceled)
 27. An integrated circuit configured to operate in a video display device, the integrated circuit comprising: input processing circuitry configured to receive incoming audio-video signal comprising an audio-video data stream having embedded timing information associated with the audio-video data of the audio-video data stream and convert the audio-video data stream into an output signal; timing controller configured to receive the different audio-video signal comprising: timing extraction circuitry for receiving the output signal comprising a stream of data symbols, the circuitry configured to identify a timing pattern for the output signal using the embedded timing information; a set of symbol buffers configured to receive the data symbols of the output signal; a scheduler configured to populate the set of symbol buffers with the data symbols in a pattern consistent with the embedded timing information; and timing control circuitry configured to support a display device for displaying the output signal, wherein the timing control circuitry is arranged to forward the data symbols from the symbol buffers at a specified time associated with characteristics of the display device.
 28. The integrated circuit of claim 27, wherein the timing extraction circuitry uses timing information encoded into a main stream attribute identifier of the output signal to identify the blanking pattern for the output signal.
 29. The integrated circuit of claim 28, wherein the scheduler uses the timing information encoded into a main stream attribute identifier to identify horizontal line ends and frame ends for the output signal and wherein the scheduler populates the set of symbol buffers with the data symbols arranged in a series of lines associated with a video frame.
 30. The integrated circuit of claim 29, wherein each symbol buffer is associated with a transmitter unit for forwarding symbols from the symbol buffer to a display device.
 31. The integrated circuit of claim 29, wherein each symbol buffer is associated with a transmitter unit of a set of transmitter units for forwarding symbols from the symbol buffer to a display device in a line by line fashion wherein each line comprises the symbols comprising a horizontal line of a frame.
 32. The integrated circuit of claim 31, wherein the timing control circuitry instructs the transmitter units to send a line of data from the buffer to column drivers of the display in accord with a schedule of the timing circuitry.
 33. The integrated circuit of claim 32, wherein the timing control circuitry schedule is associated with display characteristics of the display device that displays the data.
 34. The integrated circuit of claim 31, wherein the integrated circuit is configured to output the symbols to a plurality of column drivers of the display.
 35. The integrated circuit page of claim 32, wherein each transmitter unit is arranged to establish a point to point connection with an associated column driver of the display device.
 36. The integrated circuit of claim 32, wherein each transmitter unit of the set of transmitter units is arranged to establish a point to point connection with an associated column driver of the display device using a plurality of parallel connections such that each deliver a portion of the video signal to an associated one of a plurality of column drivers of the display.
 37. The integrated circuit of claim 35, wherein each symbol buffer is arranged to receive a low-voltage differential signal (LVDS) data stream from the scheduler using a pair of conductive lines per buffer.
 38. The integrated circuit of claim 37, wherein each symbol buffer is arranged to connect with an associated column driver of a display using a pair of conductive lines.
 39. The integrated circuit of claim 36, wherein the integrated circuit is integrated into a display device.
 40. The integrated circuit of claim 36, wherein the integrated circuit is integrated into a display device and further includes the plurality of parallel connections and the plurality of column drivers of the display.
 41. A method of processing video data in an audio-video system, the method comprising: receiving an audio-video data stream including video signal and embedded timing information associated with the audio-video data of the data stream; converting the audio-video data stream input into an output signal; identifying a timing pattern for the output signal using the embedded timing information; populating a set of symbol buffers with the data symbols in a pattern consistent with the embedded timing information; and forwarding the data symbols from the symbol buffers to a display device.
 42. The method of claim 41, wherein identifying a timing pattern for the output signal using the embedded timing information comprises identifying a blanking pattern for the video signal using the blanking start and blanking stop indicators.
 43. The method of claim 42, wherein the identifying of a blanking pattern for the video signal using the timing information comprises identifying a main stream attribute identifier in the video signal and extracting the timing information encoded into the main stream attribute identifier to identify the blanking pattern for the video signal.
 44. The method of claim 43, wherein the populating of the set of symbol buffers comprises populating the buffers in line by line fashion, wherein each line comprises a horizontal line of an audio video frame and wherein each buffer contains a portion of the line.
 45. The method of claim 44, wherein the forwarding of the data symbols from the symbol buffers to a display device is conducted such that each buffer forwards a portion of the line to an associated column driver of the display device in a plurality of parallel point to point connections between each buffer and the associated column driver.
 46. A computer implementable method for transmitting audio video data, the method embodied on a tangible computer readable media and comprising non-transitory computer readable instructions for: receiving an audio-video data stream having including video signal and embedded timing information associated with the audio-video data of the data stream; converting the audio-video data stream input into an output signal; identifying a timing pattern for the output signal using the embedded timing information; populating a set of symbol buffers with the data symbols in a pattern consistent with the embedded timing information; and forwarding the data symbols from the symbol buffers to a display device.
 47. The computer implementable method of claim 46, wherein the instructions for identifying a timing pattern for the output signal using the embedded timing information comprises identifying a blanking pattern for the video signal using the blanking start and blanking stop indicators.
 48. The computer implementable method of claim 47, wherein the instructions for identifying of a blanking pattern for the video signal using the timing information further comprise identifying a main stream attribute identifier in the video signal and extracting the timing information encoded into the main stream attribute identifier to identify the blanking pattern for the video signal.
 49. The computer implementable method of claim 48, wherein the instructions for populating the set of symbol buffers comprises populating the buffers in line by line fashion wherein each line comprises a horizontal line of an audio video frame and wherein each buffer contains a portion of the line.
 50. The computer implementable method of claim 49, wherein the instructions for forwarding of the data symbols from the symbol buffers to a display device are conducted such that each buffer forwards a portion of the line to an associated column driver of the display device in a plurality of parallel point to point connections between each buffer and the associated column driver.
 51. The computer implementable method of claim 46, wherein the instructions are implemented on an integrated circuit of display system.
 52. The computer implementable method of claim 46, wherein the computer readable instructions are implemented as firmware on an integrated circuit. 